手机版 | 每日签到 | 登录 | 注册 | 留言 | 设首页 | 加收藏
获取积分
FPGA Prototyping By verilog Examples\FPGA Prototyping By verilog Examples.pdf

....................................\fpga_vlog_src\ch01\list_ch01_01_eq1.v

....................................\.............\....\list_ch01_02_eq1_implicit.v

....................................\.............\....\list_ch01_03_eq2_sop.v

....................................\.............\....\list_ch01_04_eq2.v

....................................\.............\....\list_ch01_05_eq1_primitive.v

....................................\.............\....\list_ch01_06_eq1_udp.v

....................................\.............\....\list_ch01_07_eq2_tb.v

....................................\.............\...2\list_ch02_01_eq1.v

....................................\.............\....\list_ch02_02_eq2.v

....................................\.............\....\list_ch02_03_eq2_tb.v

....................................\.............\....\list_eq2_s3.ucf

....................................\.............\...3\list_ch03_01_eq1_always.v

....................................\.............\....\list_ch03_02_and_block_assign.v

....................................\.............\....\list_ch03_03_and_cont_assign.v

....................................\.............\....\list_ch03_04_prio_encoder_if.v

....................................\.............\....\list_ch03_05_decoder_2_4_if.v

....................................\.............\....\list_ch03_06_decoder_2_4_case.v

....................................\.............\....\list_ch03_07_prio_encoder_case.v

....................................\.............\....\list_ch03_08_prio_encoder_casez.v

....................................\.............\....\list_ch03_09_adder_carry_hard_lit.v

....................................\.............\....\list_ch03_10_adder_carry_local_par.v

....................................\.............\....\list_ch03_11_adder_carry_para.v

....................................\.............\....\list_ch03_12_adder_insta.v

....................................\.............\....\list_ch03_13_adder_carry_95.v

....................................\.............\....\list_ch03_14_hex_to_sseg.v

....................................\.............\....\list_ch03_15_hex_to_sseg_test.v

....................................\.............\....\list_ch03_16_sign_mag_addt.v

....................................\.............\....\list_ch03_17_sm_add_test.v

....................................\.............\....\list_ch03_18_barrel_shifter_case.v

....................................\.............\....\list_ch03_19_barrel_shifter_stage.v

....................................\.............\....\list_ch03_20_shifter_test.v

....................................\.............\....\list_ch03_21_fp_adder.v

....................................\.............\....\list_ch03_22_fp_adder_test.v

....................................\.............\....\list_ch04_13_disp_mux.v

....................................\.............\...4\list_ch04_01_d_ff.v

....................................\.............\....\list_ch04_02_d_ff_reset.v

....................................\.............\....\list_ch04_03_d_ff_en_1seg.v

....................................\.............\....\list_ch04_04_d_ff_en_2seg.v

....................................\.............\....\list_ch04_05_reg_reset.v

....................................\.............\....\list_ch04_06_reg_file.v

....................................\.............\....\list_ch04_07_free_run_shift_reg.v

....................................\.............\....\list_ch04_08_univ_shift_reg.v

....................................\.............\....\list_ch04_09_free_run_bin_counter.v

....................................\.............\....\list_ch04_10_univ_bin_counter.v

....................................\.............\....\list_ch04_11_mod_m_counter.v

....................................\.............\....\list_ch04_12_bin_counter_tb.v

....................................\.............\....\list_ch04_13_disp_mux.v

....................................\.............\....\list_ch04_14_disp_mux_t
当前位置: 网站首页 > FPGA > FPGA综合 > 源码下载 当前位置: FPGA综合 > 源码下载

通过Verilog例子了解FPGA原型设计(书和源码)

时间:2019-10-16    点击: 次    - 小 + 大

上一篇:uvm简单例程,DUT为Verilog小程序

下一篇:没有了

湘ICP备19004062号  |   联系站长:biguo100@qq.com  |  
Copyright © 2002-2019 Biguo100 版权所有